Last August, Intel unveiled more details about its 90-nm process used to build record-breaking silicon structures and memory chips.
Volume manufacturing with a 90-nm process using 300-mm wafers is expected to start in 2003.
This new advanced process combines higher-performance, lower-power transistors (transistors measuring only 50 nm in length), strained silicon, high-speed copper interconnects (The process also integrates a new carbon-doped oxide (CDO) dielectric material) and a new low-k dielectric material.
According to Intel’s senior vice president and general manager, Dr Sunlin Chou, this process allows Intel to make advanced products and reduce manufac-turing costs.
In February, Intel unveiled 52-Mbit SRAM chips manufactured using the 90nm process. In a chip pack, 330 million transistors are included and the area measures only 109-mm2.
The process integrates seven layers of high-speed copper interconnects, which increase processor performance. A combination of 248 nm and 193 nm wavelength lithography equipment is used for this process. The giant company expects to reduce equipment costs reusing 75% of its 0.13-µm tools on 300-mm wafers. Intel will transfer the 90-nm process to 300-mm manufacturing fabs starting next year.