MINATEC

Context of the work :

Context of the work :

The silicon nanowire MOSFETs (single wire or 3D stack) are a promising alternative to carry on the scaling and to further increase the integration density on chip, as well as the transistors performance. The surrounding gate and a diameter of only tenth of nanometers provide a better electrostatic control of the conduction channel, by reducing the short channel effects. These new architectures come along with the introduction of new materials (high permittivity oxide, metal gate …) in order to optimize the electrical properties of the devices. The specificity of the nanowire FETS relies mainly on the surrounding gate and the 2D quantum confinement. The complexity of these structures (1D carrier transport, interface roughness, multiple crystallographic orientations), added to the impact of the gate materials (defects and charges due to the high-k oxide and nitrided gate), leads to a strong modification of the electronic properties as compared to standard planar architectures. The challenge is to achieve a better understanding of the device operation and to build physical models to describe it, in order to evaluate the potentialities and the performance of nanowire transistors.

Objectives:

The aim of the thesis is to study the transport properties of the nanowire (NWs) MOSFETs, in particular to understand the scattering mechanisms limiting the drain current in linear and in saturation regime.

The work relies on electrical measurements – to develop or to adapt to the specific NW MOSFETs archtitecture –, and the extraction of fundamental parameters from the experimental data (equivalent oxide thickness, access resistance, inversion carrier density…). Advanced measurement techniques, such as pulsed drain current, low temperature measurements or magnetoresistance measurements, will help to achieve the more complete characterization as possible of the these innovative devices (mobility extraction, interface traps density in the gate oxide, ballisticity rate evaluation…). The originality of the work consists in the possibility of exploring the piezoresistivity properties of these devices, by studying the impact of a mechanical strain (applied by a four-point bending fixture for example) on the electronic properties. A special attention will be given to parameters like the carrier mobility or the mean free path in the channel, the access resistance, or the injection velocity, which are determinant in order to optimize the electrical performance.

Analytical models will be built from experimental data, to describe the different physical effects evidenced in NW MOSFETS. The models will include the quantum effects inherent to the 2D confinement of these devices. Numerical transport simulations (like MONTE-CARLO,…) could be used to support the results and to deal with some scattering mechanisms such as the interface roughness scattering which plays an important role. These analytical models, based on physics, will provide the starting material for TCAD and compact modelling, needed for circuit simulation.

Comparison with more simple fully-depleted silicon-on-insulator (FD-SOI) planar structures will bring physical mechanisms occurring in NW to light, such as the effect of the crystallographic orientation or the impact of the technological processes, and will also help to rate the performance of the NW FETs.

The work will be done within the electrical characterization and simulation laboratory, in strong collaboration with the device integration team of CEA-Léti, and in collaboration with external simulation labs (CNRS). Solid knowledge in solid-state physics and in semiconductor physics is required.