MINATEC

 
Background

 
Background
Today new technologies for CMOS nanoelectronics are developed in CEA-Leti. Among them, the Fully Depleted Silicon On Insulator technology (FDSOI) is the most promising one. The main interest of this technology arises from its capability to make transistors at the nanometer scale with a very low variability of the threshold voltage Vt. A very low variability is very suitable for the nodes 32nm and below since it ensures the functionality (high yield) of elementary cells like SRAM and Ring oscillator. Obtaining a low variability is very challenging with standard bulk technology
 However, the reliability of these cells and of more complex circuits driving these memories still is unknown. Therefore it is essential to better understand and model the degradation of the circuits integrating these memory cells in order to design and build low cost circuits intrinsically more robust;
 
This work
In this postdoc, the reliability of elementary SRAM cells used as memories for microprocessor will be largely investigated. Firstly, the student will characterize electrically the FDSOI SRAM cells made in Leti, and, more precisely, their degradation under an intensive use of these cells. This will allow us to understand how the standard reliability mechanisms responsible for the degradations of elementary transistors like NBTI and Hot Carriers effects impact the memories performance (Write and read margin,..). This work will also enable to build a compact failure model of the cell which will depend on the cell operating voltages and of its utilisation rate. At this stage, the LFSE laboratory (Embedded Circuits Reliability Laboratory) will provide to the student key elements as chronograms and standard utilisation rate of the cell.
This work will be done on basic 6T cell. A more accurate validation of the model will also be done on a matrix with several thousands of transistors. The variability from one cell to another will also be investigated and incorporated in this model. Next such a model will be integrated in a tool developed by the LFSE laboratory of CEA –List in Saclay to evaluate the global reliability of a complex circuit using intensively these SRAM cells. The student will have to participate to the implementation of the model in the LFSE simulation tool.
 Finally this initial work will be extended to other elementary cells and circuit blocks in order to obtain a more realistic idea of the reliability of a circuit made in FDSOI technology.
The job will take place in Grenoble in the electrical characterization laboratory of the CEA-Leti. This work will be done in close collaboration with the LFSE laboratory in Saclay
 
Working group

Laboratory/Department

CEA-LETI – DRT/DCOS/
 

Address

CEA/GRENOBLE, MINATEC Campus, 17 rue des Martyrs
38054 Grenoble CEDEX 9 France
 

Technical contact
Garros Xavier
04 38 78 92 44                          EMail : xavier.garros@cea.fr